Memory

ABSTRACT

A memory capable of reducing the memory cell size is provided. In this memory, a first gate electrode of a first selection transistor and a second gate electrode of a second selection transistor are provided integrally with a word line, and arranged to obliquely extend with respect to the longitudinal direction of a first impurity region on a region formed with memory cells and to intersect with the first impurity region on regions formed with the first selection transistor and the second selection transistor in plan view.

REFERENCE TO RELATED APPLICATION

This is a continuation-in-part application of U.S. patent application Ser. No. 11/073,897 submitted on Mar. 8, 2005.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a memory, and more particularly, it relates to a memory such as a mask ROM.

2. Description of the Background Art

In general, a mask ROM is known as an exemplary memory, as disclosed in Japanese Patent Laying-Open No. 5-275656 (1993), for example.

FIG. 34 is a plane layout diagram showing the structure of a conventional contact-type mask ROM. FIG. 35 is a sectional view of the conventional contact-type mask ROM taken along the line 500-500 in FIG. 34. Referring to FIGS. 34 and 35, a plurality of impurity regions 202 containing an impurity diffused therein are formed on the upper surface of a substrate 201 at prescribed intervals in the conventional contact-type mask ROM. A word line 204 functioning as a gate electrode is formed on an upper surface portion of the substrate 201 corresponding to a clearance between each adjacent pair of impurity regions 202 through a gate insulating film 203. This word line 204, the gate insulating film 203 and the corresponding pair of impurity regions 202 form each transistor 205. A first interlayer dielectric film 206 is formed to cover the upper surface of the substrate 201 and the word lines 204. The first interlayer dielectric film 206 has contact holes 207 formed in correspondence to the respective impurity regions 202, and first plugs 208 are embedded in the contact holes 207 to be connected to the impurity regions 202 respectively.

Source lines (GND lines) 209 and connection layers 210 are provided on the first interlayer dielectric film 206, to be connected to the first plugs 208. Each transistor 205 is provided every memory cell 211. A second interlayer dielectric film 212 is formed on the first interlayer dielectric film 206 to cover the source lines (GND lines) 209 and the connection layers 210. Contact holes 213 are formed in regions of the second interlayer dielectric film 212 located on prescribed ones of the connection layers 210, while second plugs 214 are embedded in the contact holes 213. Bit lines 215 are formed on the second interlayer dielectric film 212, to be connected to the second plugs 214. Thus, the bit lines 215 are connected with the impurity regions 202 of the transistors 205.

In the conventional contact-type mask ROM, those of the transistors 205 provided with the second plugs 214 are connected (contacted) to the corresponding bit lines 215. Each memory cell 211 stores data “0” or “1” in response to whether or not the transistor 205 included therein is connected to the corresponding bit line 215.

In the conventional mask ROM shown in FIG. 34, however, the memory cell size is disadvantageously increased due to the transistors 205 provided in correspondence to the respective memory cells 211.

SUMMARY OF THE INVENTION

The present invention has been proposed in order to solve the aforementioned problem, and an object thereof is to provide a memory capable of reducing the memory cell size.

In order to attain the aforementioned object, a memory according to a first aspect of the present invention comprises a memory cell array region including a plurality of memory cells arranged in the form of a matrix, a first selection transistor and a second selection transistor provided for the respective ones of the plurality of memory cells, a first impurity region functioning as an electrode partially constituting each memory cell while functioning also as one of source/drain regions of the first selection transistor and the second selection transistor, a second impurity region functioning as the other one of the source/drain regions of the first selection transistor and the second selection transistor, and a word line provided on the memory cell array region along the first impurity region. The first selection transistor and the second selection transistor share the second impurity region, a first gate electrode of the first selection transistor and a second gate electrode of the second selection transistor are provided integrally with the word line and arranged to obliquely extend with respect to the longitudinal direction of the first impurity region on a region formed with the memory cells and to intersect with the first impurity region on regions formed with the first selection transistor and the second selection transistor in plan view, and the first selection transistor and the second selection transistor divide the first impurity region.

In the memory according to the first aspect, as hereinabove described, the first gate electrode of the first selection transistor and the second gate electrode of the second selection transistor are so arranged as to obliquely extend with respect to the longitudinal direction of the first impurity region on the region formed with the memory cells and to intersect with the first impurity region on the regions formed with the first selection transistor and the second selection transistor, whereby the interval between word lines adjacent to each other in a direction perpendicular to the longitudinal direction of the first impurity region on the region formed with the memory cells can be reduced as compared with a case of constituting the gate electrode by partially arranging the word line to be perpendicular to the longitudinal direction of the first impurity region. Thus, the memory cell size can be reduced. Further, gate electrodes of selection transistors common to the plurality of memory cells can be constituted with the word line by providing the first and second gate electrodes of the first and second selection transistors for the respective ones of the plurality of memory cells integrally with the word line, whereby load capacity of the word line can be remarkably reduced as compared with a case of constituting a gate electrode of a selection transistor with the word line every memory cell. Thus, the word line can be driven at a high speed. Further, the first and second selection transistors divide the first impurity region, whereby resistance of the first impurity region can be inhibited from increase resulting from an increased length of the first impurity region. Thus, resistance loss of a current flowing through the first impurity region can be inhibited from increase. The first and second selection transistors share the second impurity region functioning as the other one of the source/drain regions, whereby the first and second selection transistors can be miniaturized as compared with a case of individually providing impurity regions functioning as other ones of the source/drain regions for the first and second selection transistors. The memory can be miniaturized also by this.

In the aforementioned memory according to the first aspect, two word lines provided along the divided first impurity region respectively are preferably connected with each other through the first gate electrode and the second gate electrode. According to this structure, the word lines can be singly linked with the divided portions of the first impurity region, whereby the number of word lines can be inhibited from increase dissimilarly to a case of providing word lines for the plurality of divided portions of the first impurity region respectively.

In the aforementioned memory according to the first aspect, the first impurity region and the second impurity region are preferably formed by performing ion implantation into a semiconductor substrate through the first gate electrode and the second gate electrode serving as masks. According to this structure, the first and second impurity regions can be simultaneously formed through a single step of performing ion implantation on the semiconductor substrate, whereby the fabrication process can be simplified.

In the aforementioned memory according to the first aspect, regions of the first impurity region and the second impurity region at least in the vicinity of portions intersecting with the first gate electrode on the region formed with the first selection transistor are preferably arranged to extend along the longitudinal direction of the first impurity region on the region formed with the memory cells in plan view, and regions of the first impurity region and the second impurity region at least in the vicinity of portions intersecting with the second gate electrode on the region formed with the second selection transistor are preferably arranged to extend along the longitudinal direction of the first impurity region on the region formed with the memory cells in plan view. According to this structure, the first gate electrode arranged to obliquely extend with respect to the longitudinal direction of the first impurity region on the region formed with the memory cells in plan view can be easily arranged to intersect with the first impurity region on the region formed with the first selection transistor arranged to extend along the longitudinal direction of the first impurity region on the region formed with the memory cells. Further, the second gate electrode arranged to obliquely extend with respect to the longitudinal direction of the first impurity region on the region formed with the memory cells in plan view can be easily arranged to intersect with the second impurity region on the region formed with the second selection transistor arranged to extend along the longitudinal direction of the first impurity region on the region formed with the memory cells.

In the aforementioned memory according to the first aspect, regions of the first impurity region and the second impurity region at least in the vicinity of portions intersecting with the first gate electrode on the region formed with the first selection transistor are preferably arranged to obliquely extend with respect to the longitudinal direction of the first impurity region on the region formed with the memory cells in plan view, and regions of the first impurity region and the second impurity region at least in the vicinity of portions intersecting with the second gate electrode on the region formed with the second selection transistor are preferably arranged to obliquely extend with respect to the longitudinal direction of the first impurity region on the region formed with the memory cells in plan view. According to this structure, the first impurity region and the first gate electrode intersect with each other in obliquely inclined states in plan view on the region formed with the first selection transistor, whereby the first impurity region and the first gate electrode can intersect with each other at a deeper angle on the region formed with the first selection transistor. Further, the first impurity region and the second gate electrode intersect with each other in obliquely inclined states in plan view on the region formed with the second selection transistor, whereby the first impurity region and the second gate electrode can intersect with each other at a deeper angle on the region formed with the second selection transistor. As hereinabove described, the first impurity region can intersect with the first and second gate electrodes at deeper angles on the regions formed with the first and second selection transistors respectively, whereby the lengths of the regions formed with the first and second selection transistors can be reduced along the longitudinal direction of the word line. Therefore, the sizes of the selection transistors can be reduced, whereby the memory can be further miniaturized. In this case, the regions of the first impurity region and the second impurity region at least in the vicinity of the portions intersecting with the first gate electrode on the region formed with the first selection transistor may be arranged to obliquely extend at an angle of not more than about 40° with respect to the longitudinal direction of the first impurity region on the region formed with the memory cells in plan view, and the regions of the first impurity region and the second impurity region at least in the vicinity of the portions intersecting with the second gate electrode on the region formed with the second selection transistor may be arranged to obliquely extend at an angle of not more than about 40° with respect to the longitudinal direction of the first impurity region on the region formed with the memory cells in plan view.

In the aforementioned structure in which the regions of the first and second impurity regions at least in the vicinity of the portions intersecting with the first gate electrode on the region formed with the first selection transistor and the regions of the first and second impurity regions at least in the vicinity of the portions intersecting with the second gate electrode on the region formed with the second selection transistor are arranged to obliquely extend in plan view, the regions of the first impurity region and the second impurity region at least in the vicinity of the portions intersecting with the first gate electrode on the region formed with the first selection transistor are preferably arranged to obliquely extend oppositely to the oblique longitudinal direction of the first gate electrode in plan view, and the regions of the first impurity region and the second impurity region at least in the vicinity of the portions intersecting with the second gate electrode on the region formed with the second selection transistor are preferably arranged to obliquely extend oppositely to the oblique longitudinal direction of the second gate electrode in plan view. According to this structure, the first gate electrode and the first impurity region obliquely extending in opposite directions in plan view as well as the second gate electrode and the first impurity region obliquely extending in opposite directions in plan view can easily intersect with each other.

In the aforementioned structure in which the regions of the first and second impurity regions at least in the vicinity of the portions intersecting with the first gate electrode on the region formed with the first selection transistor and the regions of the first and second impurity regions at least in the vicinity of the portions intersecting with the second gate electrode on the region formed with the second selection transistor are arranged to obliquely extend in plan view, the first gate electrode and the second gate electrode adjacent to each other are preferably connected with each other through a connecting portion, an edge of the connecting portion opposite to the second impurity region and an edge of the first impurity region opposite to the word line on the region formed with the memory cells are preferably substantially aligned with each other, and an edge of the second impurity region opposite to the connecting portion and an edge of the word line opposite to the first impurity region on the region formed with the memory cells are preferably substantially aligned with each other. According to this structure, the edge of the connecting portion opposite to the second impurity region can be inhibited from projecting beyond the first impurity region on the region formed with the memory cells while the edge of the second impurity region opposite to the connecting portion can be inhibited from projecting beyond the word line on the region formed with the memory cells on the outer peripheral portion of the memory cell array region. Thus, the memory cell array region can be inhibited from size increase.

In this case, the first gate electrode, the connecting portion and the second gate electrode may be arranged to have U shapes in plan view, and the first impurity region and the second impurity region on the regions formed with the first selection transistor and the second selection transistor may be arranged to have inverted U shapes intersecting with the U shapes of the first gate electrode, the connecting portion and the second gate electrode in plan view.

In the aforementioned memory according to the first aspect, the width of the word line provided along the first impurity region in a direction substantially perpendicular to the longitudinal direction of the first impurity region on the region formed with the memory cells is preferably smaller than the width of a portion around the center of the first gate electrode in a direction substantially perpendicular to the longitudinal direction of the first gate electrode and the width of a portion around the center of the second gate electrode in a direction substantially perpendicular to the longitudinal direction of the second gate electrode. According to this structure, the width of the word line provided along the first impurity region in the direction substantially perpendicular to the longitudinal direction of the first impurity region on the region formed with the memory cells can be reduced while ensuring a prescribed width in the direction substantially perpendicular to the longitudinal direction of the first and second gate electrodes when forming the word line and the first and second gate electrodes integrally with each other. Thus, the dimension of the memory cell array region can be reduced in the direction perpendicular to the longitudinal direction of the first impurity region while ensuring prescribed widths of the first and second gate electrodes.

In the aforementioned memory according to the first aspect, the width of a portion of the first gate electrode connected with the word line in a direction substantially perpendicular to the longitudinal direction of the first gate electrode is preferably smaller than the width of a portion around the center of the first gate electrode in the direction substantially perpendicular to the longitudinal direction of the first gate electrode, and the width of a portion of the second gate electrode connected with the word line in a direction substantially perpendicular to the longitudinal direction of the second gate electrode is smaller than the width of a portion around the center of the second gate electrode in the direction substantially perpendicular to the longitudinal direction of the second gate electrode. According to this structure, the width of the portion of the first gate electrode connected with the word line in the direction substantially perpendicular to the longitudinal direction of the first gate electrode can be reduced, whereby the small-width portion of the first gate electrode connected with the word line can be arranged not to interfere with other first gate electrodes adjacently arranged in the vicinity of the portion of the first gate electrode connected with the word line. Further, the width of the portion of the second gate electrode connected with the word line in the direction substantially perpendicular to the longitudinal direction of the second gate electrode can also be reduced, whereby the small-width portion of the second gate electrode connected with the word line can be arranged not to interfere with other second gate electrodes adjacently arranged in the vicinity of the portion of the second gate electrode connected with the word line.

In this case, two opposite sides of the first gate electrode preferably include a portion having a first angle with respect to the longitudinal direction of the first impurity region on the region formed with the memory cells and another portion having a second angle smaller than the first angle in plan view, and two opposite sides of the second gate electrode preferably include a portion having the first angle with respect to the longitudinal direction of the first impurity region on the region formed with the memory cells and another portion having the second angle smaller than the first angle in plan view. According to this structure, the width in the vicinity of the portion of the first gate electrode (second gate electrode) connected with the word line in the direction substantially perpendicular to the longitudinal direction of the first gate electrode (second gate electrode) can be easily rendered smaller than the width in the vicinity of the center of the first gate electrode (second gate electrode) in the direction substantially perpendicular to the longitudinal direction of the first gate electrode (second gate electrode) by arranging the portions of the two opposite sides of the first gate electrode (second gate electrode) having the first and second angles respectively so that the width is reduced from the vicinity of the center of the first gate electrode (second gate electrode) toward the portion of the first gate electrode (second gate electrode) connected with the word line in the direction substantially perpendicular to the longitudinal direction of the first gate electrode (second gate electrode).

In the aforementioned memory according to the first aspect, the plurality of memory cells preferably include single diodes respectively, and the first impurity region of a first conductivity type preferably functions as a common first electrode for the diodes of the plurality of memory cells. According to this structure, the plurality of memory cells including single diodes respectively can be reduced in size as compared with a case of including single transistors respectively. Further, the first impurity region functions as the common first electrode for the diodes of the plurality of memory cells, so that the first impurity region can be employed in common for the diodes of the plurality of memory cells. Thus, the structure of and the fabrication process for the memory cell array region can be simplified.

A memory according to a second aspect of the present invention comprises a memory cell array region including a plurality of memory cells arranged in the form of a matrix, a first selection transistor and a second selection transistor provided for the respective ones of the plurality of memory cells, a first impurity region functioning as an electrode partially constituting each memory cell while functioning also as one of source/drain regions of the first selection transistor and the second selection transistor, a second impurity region functioning as the other one of the source/drain regions of the first selection transistor and the second selection transistor and a word line provided on the memory cell array region along the first impurity region. The first selection transistor and the second selection transistor share the second impurity region, a first gate electrode of the first selection transistor and a second gate electrode of the second selection transistor are provided integrally with the word line and arranged to obliquely extend with respect to the longitudinal direction of the first impurity region on a region formed with the memory cells and to intersect with the first impurity region on regions formed with the first selection transistor and the second selection transistor in plan view, the first selection transistor and the second selection transistor divide the first impurity region, regions of the first impurity region and the second impurity region at least in the vicinity of portions intersecting with the first gate electrode on the region formed with the first selection transistor are arranged to obliquely extend with respect to the longitudinal direction of the first impurity region on the region formed with the memory cells in plan view, and regions of the first impurity region and the second impurity region at least in the vicinity of portions intersecting with the second gate electrode on the region formed with the second selection transistor are arranged to obliquely extend with respect to the longitudinal direction of the first impurity region on the region formed with the memory cells in plan view.

In the memory according to the second aspect, as hereinabove described, the first gate electrode of the first selection transistor and the second gate electrode of the second selection transistor are so arranged as to obliquely extend with respect to the longitudinal direction of the first impurity region on the region formed with the memory cells and to intersect with the first impurity region on the regions formed with the first selection transistor and the second selection transistor, whereby the interval between word lines adjacent to each other in a direction perpendicular to the longitudinal direction of the first impurity region on the region formed with the memory cells can be reduced as compared with a case of constituting the gate electrode by partially arranging the word line to be perpendicular to the longitudinal direction of the first impurity region. Thus, the memory cell size can be reduced. Further, gate electrodes of selection transistors common to the plurality of memory cells can be constituted with the word line by providing the first and second gate electrodes of the first and second selection transistors for the respective ones of the plurality of memory cells integrally with the word line, whereby load capacity of the word line can be remarkably reduced as compared with a case of constituting a gate electrode of a selection transistor with the word line every memory cell. Thus, the word line can be driven at a high speed. Further, the first and second selection transistors divide the first impurity region, whereby resistance of the first impurity region can be inhibited from increase resulting from an increased length of the first impurity region. Thus, resistance loss of a current flowing through the first impurity region can be inhibited from increase. The first and second selection transistors share the second impurity region functioning as the other one of the source/drain regions, whereby the first and second selection transistors can be miniaturized as compared with a case of individually providing impurity regions functioning as other ones of the source/drain regions for the first and second selection transistors. The memory can be miniaturized also by this.

In the memory according to the second aspect, further, the regions of the first and second impurity regions at least in the vicinity of the portions intersecting with the first gate electrode on the region formed with the first selection transistor are arranged to obliquely extend with respect to the longitudinal direction of the first impurity region on the region formed with the memory cells in plan view so that the first impurity region and the first gate electrode intersect with each other in obliquely inclined states in plan view on the region formed with the first selection transistor, whereby the first impurity region and the first gate electrode can intersect with each other at a deeper angle on the region formed with the first selection transistor. Further, the regions of the first and second impurity regions at least in the vicinity of the portions intersecting with the second gate electrode on the region formed with the second selection transistor are arranged to obliquely extend with respect to the longitudinal direction of the first impurity region on the region formed with the memory cells in plan view so that the first impurity region and the second gate electrode intersect with each other in obliquely inclined states in plan view on the region formed with the second selection transistor, whereby the first impurity region and the second gate electrode can intersect with each other at a deeper angle on the region formed with the second selection transistor. As hereinabove described, the first impurity region can intersect with the first and second gate electrodes at deeper angles on the regions formed with the first and second selection transistors respectively, whereby the lengths of the regions formed with the first and second selection transistors can be reduced along the longitudinal direction of the word line. Therefore, the sizes of the selection transistors can be reduced, whereby the memory can be further miniaturized.

The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit diagram showing the structure of a mask ROM according to a first embodiment of the present invention;

FIG. 2 is a plane layout diagram showing the structure of the mask ROM according to the first embodiment shown in FIG. 1;

FIG. 3 is a sectional view of the mask ROM according to the first embodiment taken along the line 100-100 in FIG. 2;

FIG. 4 is an enlarged plan view of a region A, shown by broken lines in FIG. 2, of the mask ROM according to the first embodiment;

FIGS. 5 and 6 are circuit diagrams for illustrating effects of the mask ROM according to the first embodiment of the present invention;

FIGS. 7 to 13 are sectional views for illustrating a fabrication process for the mask ROM according to the first embodiment of the present invention;

FIG. 14 is a sectional view for illustrating the structure of a mask ROM according to a first modification of the first embodiment of the present invention;

FIGS. 15 to 21 are sectional views for illustrating a fabrication process for the mask ROM according to the first modification of the first embodiment of the present invention;

FIG. 22 is a sectional view for illustrating the structure of a mask ROM according to a second first modification of the first embodiment of the present invention;

FIG. 23 is a circuit diagram showing the structure of an MRAM according to a second embodiment of the present invention;

FIGS. 24 and 25 are model diagrams for illustrating the structure of a TMR element employed for the MRAM according to the second embodiment shown in FIG. 23;

FIG. 26 is a sectional view showing the structure of a memory cell array of the MRAM according to the second embodiment shown in FIG. 23;

FIG. 27 is a sectional view of the memory cell array of the MRAM according to the second embodiment taken along the line 150-150 in FIG. 26;

FIG. 28 is another sectional view of the memory cell array of the MRAM according to the second embodiment taken along the line 200-200 in FIG. 26;

FIG. 29 is a sectional view showing the structure of a memory cell array of an MRAM according to a modification of the second embodiment;

FIG. 30 is a sectional view of the memory cell array of the MRAM according to the modification of the second embodiment taken along the line 250-250 in FIG. 29;

FIG. 31 is another sectional view of the memory cell array of the MRAM according to the modification of the second embodiment taken along the line 300-300 in FIG. 29;

FIG. 32 is a plane layout diagram showing the structure of a mask ROM according to a third embodiment of the present invention;

FIG. 33 is an enlarged plan view showing a region D, illustrated with broken lines, of the mask ROM according to the third embodiment shown in FIG. 32 in an enlarged manner;

FIG. 34 is a plane layout diagram showing the structure of an exemplary conventional mask ROM; and

FIG. 35 is a sectional view of the exemplary conventional mask ROM taken along the line 500-500 in FIG. 34.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Embodiments of the present invention are now described with reference to the drawings.

First Embodiment

The structure of a mask ROM according to a first embodiment of the present invention is described with reference to FIGS. 1 to 4.

As shown in FIG. 1, the mask ROM according to the first embodiment comprises an address input circuit 1, a row decoder 2, a column decoder 3, a sense amplifier 4, an output circuit 5 and a memory cell array 6. The address input circuit 1, the row decoder 2, the column decoder 3, the sense amplifier 4 and the output circuit 5 constitute a peripheral circuit. The address input circuit 1 externally receives a prescribed address, thereby outputting address data to the row decoder 2 and the column decoder 3. A plurality of word lines (WL) 7 are connected to the row decoder 2. The row decoder 2 receives the address data from the address input circuit 1, thereby selecting a word line 7 corresponding to the received address data and raising the potential of the selected word line 7 to a high level. A plurality of bit lines (BL) 8 are connected to the column decoder 3. The column decoder 3 receives the address data from the address input circuit 1, thereby selecting a bit line 8 corresponding to the received address data and connecting the selected bit line 8 to the sense amplifier 4. The sense amplifier 4 determines and amplifies the potential of the bit line 8 selected by the column decoder 3, for outputting a high-level signal when the potential of the selected bit line 8 is at a low level while outputting a low-level signal when the potential of the selected bit line 8 is at a high level. The sense amplifier 4 includes a load circuit (not shown) raising the potential of the selected bit line 8 to a high level when the potential of this bit line 8 is not at a low level. The output circuit 5 receives the output from the sense amplifier 4, thereby outputting a signal.

A plurality of memory cells 9 are arranged on the memory cell array 6 in the form of a matrix. Each memory cell 9 includes a diode 10. The memory cell array 6 is provided with memory cells 9 including diodes 10 having anodes connected to the corresponding bit lines 8 and memory cells 9 including diodes 10 having anodes connected to none of the bit lines 8. Each memory cell 9 stores data “0” or “1” in response to whether or not the anode of the diode 10 is connected to the corresponding the bit line 8. The cathodes of the diodes 10 are connected to the drains of selection transistors 11 consisting of n-channel transistors. The selection transistors 11 have sources grounded through source lines (GND lines) 12 and gates connected to the word lines 7.

In the memory cell array 6, a plurality of n-type impurity regions 14 are provided on the upper surface of a p-type silicon substrate 13 at prescribed intervals, as shown in FIGS. 2 and 3. The p-type silicon substrate 13 is an example of the “semiconductor substrate” in the present invention, and each n-type impurity region 14 is an example of the “first impurity region” in the present invention. As shown in FIG. 3, each n-type impurity region 14 is constituted of an n-type low-concentration impurity region 14 a and an n-type impurity region 14 b formed deeper than the impurity region 14 a. The impurity region 14 a is an example of the “fourth impurity region” in the present invention, and the impurity region 14 b is an example of the “fifth impurity region” in the present invention. The impurity region 14 b has an impurity concentration slightly higher than that of the impurity region 14 a.

According to the first embodiment, a plurality of (eight) p-type impurity regions 15 are formed in each n-type impurity region 14 at prescribed intervals. Each p-type impurity region 15 and the corresponding n-type impurity region 14 form the diode 10. Thus, each n-type impurity region 14 functions as a common cathode of a plurality of diodes 10. Further, each p-type impurity region 15 is employed as the anode of the corresponding diode 10. A plurality of (eight) diodes 10 are formed in each n-type impurity region 14. In other words, each n-type impurity region 14 is employed in common for the plurality of (eight) diodes 10. When the silicon substrate 13 is included in the structure of each diode 10, a pnp bipolar transistor is parasitically constituted. In this case, the p-type impurity region 15 and the n-type impurity region 14 functioning as the anode and the cathode of the diode 10 linked to the corresponding bit line 8 respectively and the p-type silicon substrate 13 function as the emitter, the base and the collector of the bipolar transistor respectively.

According to the first embodiment, the n-type impurity region 14 functions also as the drain region of each selection transistor 11 (11 a or 11 b). The selection transistor 11 a is an example of the “first selection transistor” in the present invention, and the selection transistor 11 b is an example of the “second selection transistor” in the present invention. According to the first embodiment, each of the selection transistors 11 a and 11 b is provided for eight diodes 10 (memory cells 9). Source regions 17 of the selection transistors 11 (11 a and 11 b) are formed on both sides of the n-type impurity regions 14 at prescribed intervals.

Each source region 17 is shared by each selection transistor 11 a provided for prescribed eight memory cells 9 (diodes 10) and each selection transistor 11 b provided for other eight memory cells 9 (diodes 10) adjacent to the prescribed eight memory cells 9 (diodes 10). Each source region 17 includes an n-type low-concentration impurity region 17 a and an n-type high-concentration impurity region 17 b. The source region 17 is an example of the “second impurity region” in the present invention. The n-type low-concentration impurity region 17 a is formed on a relatively shallow region of the surface of the p-type silicon substrate 13, while the n-type high-concentration impurity region 17 b is formed on a region deeper than the n-type low-concentration impurity region 17 a. Thus, the source region 17 has an LDD (lightly doped drain) structure consisting of the n-type low- and high-concentration impurity regions 17 a and 17 b. In this source region 17, an n-type contact region 17 c is formed in the n-type low- and high-concentration impurity regions 17 a and 17 b. This n-type contact region 17 c is provided for reducing contact resistance when a first plug 23 described later is connected to the source region 17.

According to the first embodiment, the impurity concentrations of the n-type low-concentration impurity region 17 a of each source region 17 and the impurity region 14 a of each n-type impurity region 14 are identical to each other. Further, the impurity concentration of the n-type high-concentration impurity region 17 b of the source region 17 is higher than that of the impurity region 14 b of the n-type impurity region 14. In the memory cell array 6, each pair of adjacent n-type impurity regions 14 are arranged at prescribed intervals from the source region 17 common to two selection transistors 11 (11 a and 11 b) respectively. In other words, the n-type impurity regions 14 are divided on regions of the p-type silicon substrate 13 corresponding to the two selection transistors 11 (11 a and 11 b).

A gate electrode 19 (19 a or 19 b) is formed on a channel region of the p-type silicon substrate 13 between each n-type impurity region 14 and each source region 17 through a gate insulating film 18. The gate electrode 19 (19 a or 19 b) is formed integrally with the corresponding word line 7 of a polysilicon film, as shown in FIG. 2. The gate electrode 19 a is an example of the “first gate electrode” in the present invention, and the gate electrode 19 b is an example of the “second gate electrode” in the present invention. Each pair of adjacent gate electrodes 19 a and 19 b are connected with each other through a connecting portion 19 c. The gate electrode 19 a, the connecting portion 19 c and the gate electrode 19 b are arranged to have U shapes in plan view.

The word lines 7 are provided at prescribed intervals, as shown in FIG. 2. The gate electrodes 19 (19 a and 19 b) are formed by partially bending the word lines 7 to obliquely extend with respect to the longitudinal direction of the n-type impurity regions 14 in plan view, as shown in FIG. 2. The gate electrode 19 a of each selection transistor 11 a is arranged to intersect with the corresponding n-type impurity region 14 on the region formed with the selection transistor 11 a. The gate electrode 19 b of each selection transistor 11 b is arranged to intersect with the corresponding n-type impurity region 14 on the region formed with the selection transistor 11 b.Each gate electrode 19 a, each n-type impurity region 14 and each source region 17 constitute each selection transistor 11 a. Further, each gate electrode 19 b, each n-type impurity region 14 and each source region 17 constitute each selection transistor 11 b. As shown in FIG. 4, two opposite edges of each gate electrode 19 are constituted of portions B and C having angles of about 45° and about 40° respectively in the direction along each n-type impurity region 14 in plan view. Thus, the width t1 of a portion around a bent portion of each word line 7 is smaller than the width t2 of a portion around the central portion of each gate electrode 19. On each edge of the gate electrode 19, the portion B having the angle of about 45° is rendered shorter than the portion C having the angle of about 40°. According to this structure, the portions having the angle of about 40° around the bent portions of each word line 7 having the width t1 are opposed to the portions of adjacent word lines 7 having the angle of about 45° respectively while increasing the intervals between the adjacent word lines 7, whereby the bent portion of each word line 7 is inhibited from coming into contact with the adjacent word lines 7. The width t3 of a portion of each word line 7 along the longitudinal direction of each n-type impurity region 14 is rendered smaller than the width t2 of the portion around the central portion of each gate electrode 19. The widths t1, t2 and t3 of the portions of the word line 7 are in the following relation: t2>t1≈t3

As shown in FIG. 3, side wall spacers 20 of insulating films are provided on both sides of each gate electrode 19 (19 a or 19 b). A first interlayer dielectric film 21 is provided on the upper surface of the p-type silicon substrate 13, to cover the gate electrodes 19 (word lines 7) and the side wall spacers 20. Contact holes 22 are provided in regions of the first interlayer dielectric film 21 corresponding to the p-type impurity regions 15 and the n-type contact regions 17 c. First plugs 23 of W (tungsten) are embedded in the contact holes 22. Thus, the plugs 23 are connected to the p-type impurity regions 15 and the n-type contact regions 17 c.

As shown in FIG. 3, further, the source lines 12 of Al and first connection layers 24 are provided on the first interlayer insulating film 21, to be connected to the first plugs 23. In addition, a second interlayer dielectric film 25 is provided on the first interlayer dielectric film 21, to cover the source lines 12 and the first connection layers 24. Contact holes 26 are formed in regions of the second interlayer dielectric film 25 corresponding to the first connection layers 24. Second plugs 27 of W are embedded in the contact holes 26.

Second connection layers 28 of Al are provided on the second interlayer dielectric film 25, to be connected to the second plugs 27. A third interlayer dielectric film 29 is provided on the second interlayer dielectric film 25, to cover the second connection layers 28. Contact holes 30 are provided in the third interlayer dielectric film 29, and third plugs 31 of W are embedded in the contact holes 30. The third plugs 31 are connected to the second connection layers 29. The plurality of bit lines 8 of Al are provided on the third interlayer dielectric film 29 at prescribed intervals. The bit lines 8 are connected to the third plugs 31. The third plugs 31 are provided between those of the second connection layers 28 linked with prescribed p-type impurity regions 15 (anodes of the diodes 10) and the corresponding bit lines 8, while no third plugs 31 are provided between the second connection layers 28 linked with the remaining p-type impurity regions 15 (anodes of the diodes 10) and the corresponding bit lines 8. Thus, the diodes 10 include those having anodes connected to the corresponding bit lines 8 and those having anodes connected to none of the bit lines 8. In other words, the mask ROM according to the first embodiment stores data “0” or “1” in response to whether or not the contact holes 30 are provided on the third interlayer dielectric film 29.

Operations of the mask ROM according to the first embodiment are now described with reference to FIG. 1. First, a prescribed address is input in the address input circuit 1. Thus, the address input circuit 1 outputs address data responsive to the input address to the row decoder 2 and the column decoder 3 respectively. The row decoder 2 decodes the address data, thereby selecting a prescribed word line 7 corresponding to the address data. The potential of the selected word line 7 goes high, thereby turning on the selection transistor 11 having the gate connected to the selected word line 7. Therefore, the potential of the drain of the selection transistor 11 is lowered to the GND level (low level), thereby also lowering the potential of the cathode of the diode 10 employed in common with the drain of the selection transistor 11 to the GND level (low level). At this time, the potentials of the nonselected word lines 7 are held at low levels. Thus, the selection transistors 11 linked with the nonselected word lines 7 are held in OFF states.

On the other hand, the column decoder 3 receiving the address data from the address input circuit 1 selects a prescribed bit line 8 corresponding to the received address data and connects the selected bit line 8 to the sense amplifier 4. If the anode of the diode 10 of a selected memory cell 9 corresponding to the selected word line 7 and the selected bit line 8 is linked with this bit line 8, the potential of the bit line 8 is reduced to a low level through the diode 10. Thus, the low-level potential of the bit line 8 is transmitted to the sense amplifier 4. The sense amplifier 4 determines and amplifies the potential of the bit line 8, and thereafter outputs a high-level signal of reverse polarity to the low-level potential of the bit line 8. The output circuit 5 receiving the output signal from the sense amplifier 4 outputs the high-level signal. If the anode of the diode 10 of the selected memory cell 9 corresponding to the selected word line 7 and the selected bit line 8 is not linked with the bit line 8, on the other hand, no low-level potential is transmitted to the sense amplifier 4. In this case, the load circuit (not shown) provided in the sense amplifier 4 raises the potential of the bit line 8 to a high level. Thus, the sense amplifier 4 determines and amplifies the potential of the bit line 8, and thereafter outputs a high-level signal of reverse polarity to the low-level potential of the bit line 8. The output circuit 5 receiving the output signal from the sense amplifier 4 outputs the high-level signal.

In the mask ROM according to the first embodiment, each memory cell 9 is so provided with the diode 10 as to suppress false data reading resulting from a circumventive current. More specifically, a diode E shown in FIG. 5 suppresses flow of a current when the current flows along arrow D in data reading from a selected memory cell, as shown in FIG. 5. If the memory cell 9 is provided with no diode 10, however, a current flows along arrow F while circumventing another bit line in addition to a selected bit line, as show in FIG. 6. In this case, it is impossible to determine whether or not data read through the selected bit line is that stored in the selected memory cell, leading to false data reading. On the other hand, the mask ROM according to the first embodiment allows no current circumvention, to read data only from the selected memory cell 9. Thus, the mask ROM suppresses false data reading.

When the silicon substrate 13 is included in the structure of each diode 10 in the first embodiment, the pnp bipolar transistor is parasitically constituted while the p-type impurity region 15, the n-type impurity region 14 and the p-type silicon substrate 13 function as the emitter, the base and the collector of the bipolar transistor respectively. Thus, an operation of forwardly feeding a current through the diode 10 corresponds to an operation of feeding the current between the emitter and the base of the bipolar transistor. In this case, the current also flows between the emitter (p-type impurity region 15) and the collector (p-type silicon substrate 13) of the bipolar transistor. Thus, the current flowing through the bit line 8 corresponds to the sum of the current flowing between the emitter (p-type impurity region 15) and the base (n-type impurity region 14) and that flowing between the emitter (p-type impurity region 15) and the collector (p-type silicon substrate 13). The current flowing between the emitter and the collector is generated when the current flows between the emitter and the base, and hence it follows that a cell current flowing through the memory cell 9 (diode 10) is amplified. According to the first embodiment, therefore, the current flowing through the bit line 8 is inhibited from reduction by amplification of the current flowing from the p-type impurity region 15 to the p-type silicon substrate 13 also when the quantity of the current flowing from the p-type impurity region 15 serving as the anode to the impurity region 14 a of the n-type impurity region 14 is reduced due to high resistance of the n-type impurity region 14 serving as the cathode of the diode 10.

A fabrication process for the mask ROM according to the first embodiment is now described with reference to FIGS. 2, 3 and 7 to 13. Steps of forming wells and element separation regions (LOCOS and STI structures etc.) on the p-type silicon substrate 13 are omitted from the following description of the fabrication process.

As shown in FIG. 7, the word lines 7 (gate electrodes 19) of polysilicon are formed on the upper surface of the p-type silicon substrate 13 through the gate insulating films 18. The plurality of word lines 7 are formed at the prescribed intervals in plan view, as shown in FIG. 2.

As shown in FIG. 8, P (phosphorus) is ion-implanted into prescribed regions of the p-type silicon substrate 13 under conditions of implantation energy of about 50 keV and a dose (quantity of implantation) of about 3.0×201³ cm⁻² through the gate electrodes 19 serving as masks. Thus formed are the low-concentration impurity regions 14 a of the n-type impurity regions 14 and the n-type low-concentration impurity regions 17 a divided along the regions corresponding to the gate electrodes 19.

As shown in FIG. 9, an insulating film is formed to cover the overall surface and thereafter anisotropically etched, thereby forming the side wall spacers 20 of insulating films on the side surfaces of the gate electrodes 19. Thereafter resist films 32 are formed to cover the n-type low-concentration impurity regions 17 a, for thereafter ion-implanting P (phosphorus) through the gate electrodes 19, the side wall spacers 20 and the resist films 32 serving as masks under conditions of implantation energy of about 100 keV and a dose of about 3.5×201³ cm⁻². Thus, the n-type impurity regions 14 b having the impurity concentration slightly higher than that of the impurity regions 14 a are formed on regions corresponding to the n-type low-concentration impurity regions 14 a. The impurity regions 14 b are formed up to regions deeper than the impurity regions 14 a. The impurity regions 14 a and 14 b constitute the n-type impurity regions 14.

As shown in FIG. 10, resist films 33 are formed to cover the n-type impurity regions 14. Thereafter As is ion-implanted under conditions of implantation energy of about 70 keV and a dose of about 5.0×201⁵ cm⁻² through the gate electrodes 19, the side wall spacers 20 and the resist films 33 serving as masks. Thus, the n-type high-concentration impurity regions 17 b having the impurity concentration higher than that of the n-type low-concentration impurity regions 17 a are formed on regions corresponding to the n-type low-concentration impurity regions 17 a. The n-type high-concentration impurity regions 17 b are formed up to regions deeper than the n-type low-concentration impurity regions 17 a. The n-type low-concentration impurity regions 17 a and the n-type high-concentration impurity regions 17 b form the n-type source regions 17 having the LDD structure.

As shown in FIG. 11, the first interlayer dielectric film 21 is formed on the p-type silicon substrate 13, to cover the gate electrodes 19 (word lines 7) and the side wall spacers 20. Thereafter the contact holes 22 are formed on the regions of the first interlayer dielectric film 21 corresponding to the source regions 17 and the n-type impurity regions 14 by photolithography and dry etching.

As shown in FIG. 12, resist films 34 are formed to cover the regions of the first interlayer dielectric film 21 corresponding to the n-type impurity regions 14. Thereafter P (phosphorus) is ion-implanted into the source regions 17 under conditions of implantation energy of about 25 keV and a dose of about 3.0×201⁴ cm⁻² through the contact holes 22, thereby forming the n-type contact regions 17 c.

As shown in FIG. 13, resist films 35 are formed to cover the regions of the first interlayer dielectric film 21 corresponding to the source regions 17. Thereafter BF₂ is ion-implanted into the n-type impurity regions 14 under conditions of implantation energy of about 40 keV and a dose of about 2.0×201⁵ cm⁻² through the contact holes 22. Thus, the plurality of (eight) p-type impurity regions 15 are formed in each n-type impurity region 14 in correspondence to the contact holes 22. The plurality of (eight) p-type impurity regions 15 and the n-type impurity region 14 form the plurality of (eight) diodes 10 in the n-type impurity region 14. The p-type impurity regions 15 are formed up to regions slightly deeper than the impurity regions 14 a of the n-type impurity region 14.

As shown in FIG. 3, the first plugs 23 of W are formed to fill up the contact holes 22. Thus, the first plugs 23 are connected to the p-type impurity regions 15 and the n-type contact regions 17 c of the source regions 17 respectively. Then, the first connection layers 24 of Al are formed on the first interlayer dielectric film 21 to be connected to the plugs 23 linked with the p-type impurity regions 15, while the source lines 12 of Al are formed to be connected to the plugs 23 linked with the source regions 17. The second interlayer dielectric film 25 is formed on the first interlayer dielectric film 21 to cover the first connection layers 24 and the source lines 12, and the contact holes 26 are thereafter formed on the regions corresponding to the first connection layers 24. The second plugs 27 of W are embedded in the contact holes 26. The second connection layers 28 of Al are formed on the second interlayer dielectric film 25, to be connected to the second plugs 27. Thereafter the third interlayer dielectric film 29 is formed on the second interlayer dielectric film 25, to cover the second connection layers 28.

The contact holes 30 are formed on the regions of the third interlayer dielectric film 29 corresponding to the second connection layers 28, while the third plugs 31 of W are embedded in the contact holes 30. At this time, the contact holes 30 and the third plugs 31 are provided for the p-type impurity regions 15 connected to the corresponding bit lines 8, while neither contact holes 30 nor third plugs 31 are provided for the p-type impurity regions 15 connected to none of the bit lines 8. Finally, the bit lines 8 of Al are formed on the third interlayer dielectric film 29. Thus, the second connection layers 28 and the bit lines 8 are connected with each other through the third plugs 31 on the regions provided with the third plugs 31, whereby the p-type impurity regions 15 linked with the second connection layers 28 are connected to the bit lines 8. On the regions provided with no third plugs 31, on the other hand, the second connection layers 28 and the bit lines 8 are not connected with each other and hence the p-type impurity regions 15 are connected to none of the bit lines 8. Thus, the diodes 10 include those having the anodes (p-type impurity regions 15) connected to the bit lines 8 corresponding to either data “0” or “1” and those having the anodes (p-type impurity regions 15) connected to none of the bit lines 8 corresponding to either the data “1” or “0”. The memory cell array 6 of the mask ROM according to the first embodiment is formed in the aforementioned manner, as shown in FIG. 3.

According to the first embodiment, as hereinabove described, the gate electrodes 19 a and 19 b of the selection transistors 11 a and 11 b are arranged to obliquely extend with respect to the longitudinal direction of the n-type impurity regions 14 on the region formed with the memory cells 9 and to intersect with the n-type impurity regions 14 on the regions formed with the selection transistors 11 a and 11 b, whereby the intervals between the word lines 7 adjacent to each other in the direction perpendicular to the longitudinal direction of the n-type impurity regions 14 on the region formed with the memory cells 9 can be reduced as compared with a case of partially arranging the word lines 7 perpendicularly to the longitudinal direction of the n-type impurity regions 14 for constituting the gate electrodes 19. Thus, the memory cell size can be further reduced. Therefore, the mask ROM can be miniaturized.

According to the first embodiment, further, the gate electrodes 19 a and 19 b of the selection transistors 11 a and 11 b each provided for the plurality of memory cells 9 are provided integrally with the word lines 7 so that the gate electrodes 19 a and 19 b of the selection transistors 11 a and 11 b each common to the plurality of memory cells 9 can be constituted with the word lines 7, whereby the load capacity of the word lines 7 can be remarkably reduced as compared with a case of forming the gate electrode of a selection transistor every memory cell 9 with each word line 7. Thus, the word lines 7 can be driven at a high speed.

According to the first embodiment, further, the selection transistors 11 a and 11 b so divide the n-type impurity regions 14 that resistance of the n-type impurity regions 14 can be inhibited from increase resulting from an increased length of the n-type impurity regions 14. Thus, the current flowing through the n-type impurity regions 14 can be inhibited from increase of resistance loss.

According to the first embodiment, further, the selection transistors 11 a and 11 b formed to share the source region 17 can be miniaturized as compared with a case of individually providing source regions for the selection transistors 11 a and 11 b.

According to the first embodiment, further, adjacent pairs of word lines 7 provided along the divided n-type impurity regions 14 are so connected through the gate electrodes 19 a and 19 b that the word lines 7 can be singly linked to the plurality of divided n-type impurity regions 14, whereby the number of the word lines 7 can be inhibited from increase dissimilarly to a case of individually providing word lines 7 for the plurality of divided n-type impurity regions 14.

According to the first embodiment, further, the impurity regions 14 a and the n-type low-concentration impurity regions 17 a constituting the n-type impurity regions 14 and the source regions 17 respectively are formed by performing ion implantation into the p-type silicon substrate 13 through the gate electrodes 19 a and 19 b serving as masks so that the impurity regions 14 a and the n-type low-concentration impurity regions 17 a constituting the n-type impurity regions 14 and the source regions 17 respectively can be simultaneously formed through a single step of performing ion implantation into the p-type silicon substrate 13, whereby the fabrication process can be simplified.

The structure of a mask ROM according to a first modification of the first embodiment is now described with reference to FIG. 14. The first modification of the first embodiment is described with reference to a case of rendering a fabrication process for selection transistors 41 of a memory cell array and a fabrication process for a low withstand voltage n-channel transistor 42, a low withstand voltage p-channel transistor 44 and a high withstand voltage transistor 43 provided on a peripheral circuit partially in common.

As shown in FIG. 14, the mask ROM according to the first modification of the first embodiment comprises the low withstand voltage n-channel transistor 42 having a prescribed withstand voltage, the high withstand voltage transistor 43 having a withstand voltage higher than that of the low withstand voltage n-channel transistor 42 and a low withstand voltage p-channel transistor 44 having a prescribed withstand voltage provided in the peripheral circuit, in addition to a selection transistor 41.

The selection transistor 41 has n-type source/drain regions 41 a similar in structure to the n-type impurity regions 14 in the aforementioned first embodiment. The drain regions of the selection transistor 41 are formed with p-type impurity regions 15. Thus, diodes consisting of n-type impurity regions 14 and the p-type impurity regions 15 are formed in the drain regions of the selection transistor 41. On the other hand, n-type contact regions 41 c for reducing contact resistance with first plugs 23 (see FIG. 3) are formed in the source regions of the selection transistor 41. The low withstand voltage n-channel transistor 42 includes n-type source/drain regions 42 a having n-type low-concentration impurity regions 42 b containing P (phosphorus) and n-type high-concentration impurity regions 42 c containing As. The n-type low-concentration impurity regions 42 b and the n-type high-concentration impurity regions 42 c form an LDD structure. The n-type source/drain regions 42 a of the low withstand voltage n-channel transistor 42 are further provided with n-type contact regions 42 d for reducing contact resistance with first plugs 23 (see FIG. 3).

The high withstand voltage transistor 43 includes n-type source/drain regions 43 a having n-type low-concentration impurity regions 43 b containing P (phosphorus) and n-type high-concentration impurity regions 43 containing As. The n-type low-concentration impurity regions 43 b are formed to enclose the n-type high-concentration impurity regions 43 c. Thus, the n-type low-concentration impurity regions 43 b are interposed between the n-type high-concentration impurity regions 43 b and a p-type silicon substrate 13, thereby relaxing field concentration over the boundary between the n-type high-concentration impurity regions 43 b and the p-type silicon substrate 13. The n-type source/drain regions 43 a of the high withstand voltage transistor 43 are provided with n-type contact regions 43 d for reducing contact resistance with first plugs (see FIG. 3).

The low withstand voltage p-channel transistor 44 includes p-type source/drain regions 44 a containing B (boron). The p-type source/drain regions 44 a are provided with p-type contact regions 44 c for reducing contact resistance with first plugs (see FIG. 3). The low withstand voltage p-channel transistor 44 is formed in an n well 44 d formed on the p-type silicon substrate 13.

According to the first modification of the first embodiment, the n-type low-concentration impurity regions 43 b of the high withstand voltage transistor 43 have the same impurity concentration as that of n-type impurity regions 14 b of the selection transistor 41. Further, the n-type high-concentration impurity regions 43 c of the high withstand voltage transistor 43 have the same impurity concentration as that of the n-type high-concentration impurity regions 42 c of the low withstand voltage n-channel transistor 42. In addition, the n-type low-concentration impurity regions 42 b of the low withstand voltage n-channel transistor 42 have the same impurity concentration as that of n-type low-concentration impurity regions 14 a of the selection transistor 41.

A first interlayer dielectric film 21 is formed on the regions formed with the selection transistor 41, the low withstand voltage n-channel transistor 42, the high withstand voltage transistor 43 and the low withstand voltage p-channel transistor 44. Contact holes 22, 42 e, 43 e and 44 e are provided in regions of the first interlayer dielectric film 21 corresponding to the p-type impurity regions 15 and the n-type contact regions 41 c of the selection transistor 41, the n-type contact regions 42 d of the low withstand voltage n-channel transistor 42, the n-type contact regions 43 d of the high withstand voltage transistor 43 and the p-type contact regions 44 c of the low withstand voltage p-channel transistor 44 respectively. The plugs 23 are embedded in the contact holes 22, 42 e, 43 e and 44 e respectively.

A fabrication process for the mask ROM according to the first modification of the first embodiment is now described with reference to FIGS. 14 to 21.

As shown in FIG. 15, the n well 44 d is formed on the region of the p-type silicon substrate 13 for forming the low withstand voltage p-channel transistor 44. Gate electrodes 19 are formed on the p-type silicon substrate 13 through gate insulator films 18. Resist films 45 are formed to cover the regions for forming the high withstand voltage transistor 43 and the low withstand voltage p-channel transistor 44, and P (phosphorus) is thereafter ion-implanted under conditions of implantation energy of about 50 keV and a dose (quantity of implantation) of about 3.0×201³ cm⁻² through the resist films 45 serving as masks. Thus, the n-type low-concentration impurity regions 42 b of the low withstand voltage n-channel transistor 42 and the low-concentration impurity regions 14 a of the selection transistor 41 are formed at the same time.

As shown in FIG. 16, resist films 46 are formed to cover the regions for forming the low withstand voltage n-channel transistor 42 and the low withstand voltage p-channel transistor 44 as well as a region of the selection transistor 41 slightly larger than the width of the corresponding gate electrode 19, and P (phosphorus) is thereafter ion-implanted under conditions of implantation energy of about 100 keV and a dose of about 3.5×201³ cm⁻² through the resist films 46 serving as masks. Thus, the n-type low-concentration impurity regions 43 b of the high withstand voltage transistor 43 are formed. The n-type low-concentration impurity regions 43 b are formed up to regions deeper than the n-type low-concentration impurity regions 42 b of the low withstand voltage n-channel transistor 42 and the low-concentration impurity regions 14 a of the selection transistor 41. Further, the impurity regions 14 b having the impurity concentration slightly higher than that of the low-concentration impurity regions 14 a are formed on the region for forming the selection transistor 41. Thus, the n-type source/drain regions 41 a consisting of the impurity regions 14 a and 14 b are formed on the region for forming the selection transistor 41.

As shown in FIG. 17, an insulating film is formed to cover the overall surface and thereafter anisotropically etched thereby forming side wall spacers 20 of insulating films on the side surfaces of the gate electrodes 19.

As shown in FIG. 18, resist films 47 are formed to cover the regions for forming the selection transistor 41 and the low withstand voltage p-channel transistor 44, and As is thereafter ion-implanted under conditions of implantation energy of about 70 keV and a dose of about 5.0×201⁵ cm⁻² through the resist films 47 serving as masks. Thus, the n-type high-concentration impurity regions 42 c of the low withstand voltage n-channel transistor 42 and the n-type high-concentration impurity regions 43 c of the high withstand voltage transistor 43 are formed at the same time. The n-type source/drain regions 42 a consisting of the n-type low-concentration impurity regions 42 b and the n-type high-concentration impurity regions 42 c are formed on the region for forming the low withstand voltage n-channel transistor 42, while the n-type source/drain regions 43 a consisting of the n-type low-concentration impurity regions 43 b and the n-type high-concentration impurity regions 43 c are formed on the region for forming the high withstand voltage transistor 43.

As shown in FIG. 19, resist films 48 are formed to cover the regions for forming the selection transistor 41, the low withstand voltage n-channel transistor 42 and the high withstand voltage transistor 43, and BF₂ is thereafter ion-implanted under conditions of implantation energy of about 50 keV and a dose of about 2.0×201⁵ cm⁻² through the resist films 48 serving as masks. Thus, the p-type source/drain regions 44 a of the low withstand voltage p-channel transistor 44 are formed.

As shown in FIG. 20, heat treatment is so performed as to thermally diffusing the p-type impurity in the p-type source/drain regions 44 a of the low withstand voltage p-channel transistor 44. Thus, the p-type source/drain regions 44 a are formed up to portions located under the side wall spacers 20 of the low withstand voltage p-channel transistor 44. The first interlayer dielectric film 21 is formed through a process similar to that in the aforementioned first embodiment, to cover the regions for forming the selection transistor 41, the low withstand voltage n-channel transistor 42, the high withstand voltage transistor 43 and the low withstand voltage p-channel transistor 44 respectively. Then, the contact holes 22, 42 e, 43 e and 44 e are formed on the regions of the first interlayer dielectric film 21 corresponding to the n-type source/drain regions 41 a of the selection transistor 41, the n-type source/drain regions 42 a of the low withstand voltage n-channel transistor 42, the n-type source/drain regions 43 a of the high withstand voltage transistor 43 and the p-type source/drain regions 44 a of the low withstand voltage p-channel transistor 44 respectively. Resist films 49 are formed to cover regions of the first interlayer dielectric film 21 corresponding to the source regions of the selection transistor 41, the region for forming the low withstand voltage n-channel transistor 42 and the region for forming the high withstand voltage transistor 43. Thereafter BF₂ is ion-implanted under conditions of implantation energy of about 40 keV and a dose of about 2.0×201⁵ cm⁻² through the resist films 49 serving as masks. Thus, the p-type contact regions 44 c of the low withstand voltage p-channel transistor 44 and the p-type impurity regions 15 are formed at the same time. The p-type impurity regions 15 and the n-type impurity regions 14 form the diodes.

As shown in FIG. 21, resist films 50 are finally formed to cover regions of the first interlayer dielectric film 21 corresponding to the drain regions of the selection transistor 41 and the region for forming the low withstand voltage p-channel transistor 44, and P (phosphorus) is thereafter ion-implanted under conditions of implantation energy of about 25 keV and a dose of about 3.0×201⁴ cm⁻² through the resist films 50 serving as masks. Thus, the n-type contact regions 41 c, 42 d and 43 d are formed in the source regions of the selection transistor 41, the source/drain regions 42 a of the low withstand voltage n-channel transistor 42 and the source/drain regions 43 a of the high withstand voltage transistor 43 respectively. Thereafter the plugs 23 are embedded in the contact holes 22, 42 e, 43 e and 44 e respectively. Thus, the selection transistor 41, the low withstand voltage n-channel transistor 42, the high withstand voltage transistor 43 and the low withstand voltage p-channel transistor 44 are formed as shown in FIG. 14.

The remaining fabrication process according to the first modification of the first embodiment is similar to that of the aforementioned first embodiment.

According to the first modification of the first embodiment, as hereinabove described, the n-type low-concentration impurity regions 43 b of the high withstand voltage transistor 43 are formed to have the same impurity concentration as that of the n-type impurity regions 14 b of the selection transistor 41, the n-type high-concentration impurity regions 43 c of the high withstand voltage transistor 43 are formed to have the same impurity concentration as that of the n-type high-concentration impurity regions 42 c of the low withstand voltage n-channel transistor 42 and the n-type low-concentration impurity regions 42 b of the low withstand voltage n-channel transistor 42 are formed to have the same impurity concentration as that of the n-type impurity regions 14 a of the selection transistor 41, so that the n-type low-concentration impurity regions 43 b of the high withstand voltage transistor 43 can be formed through the same step as that for the impurity regions 14 b of the selection transistor 41 and the n-type high-concentration impurity regions 43 c of the high withstand voltage transistor 43 can be formed through the same step as that for the n-type high-concentration impurity regions 42 c of the low withstand voltage n-channel transistor 42. Further, the n-type low-concentration impurity regions 42 b of the low withstand voltage n-channel transistor 42 can be formed through the same step as that for the impurity regions 14 a of the selection transistor 41. In addition, the p-type impurity regions 15 constituting the diodes can be formed through the same step as that for the p-type contact regions 44 c of the low withstand voltage p-channel transistor 44. Thus, a fabrication process for forming the selection transistor 41 and the diodes on a memory cell array can be partially rendered common to that for the low withstand voltage n-channel transistor 42, the high withstand voltage transistor 43 and the low withstand voltage p-channel transistor 44 of the peripheral circuit, whereby the fabrication process is not much complicated despite provision of the selection transistor 41 and the diode.

According to a second modification of the first embodiment, a source region 41 b (17) of a selection transistor 41 can be constituted similarly to n-type source/drain regions 42 a of a low withstand voltage n-channel transistor 42, as shown in FIG. 22. In this case, low-concentration impurity regions 17 a and 14 a (see FIG. 22) of the source region 41 b (17) and a drain region 41 a (14) of the selection transistor 41 and n-type low-concentration impurity regions 42 b of the n-type source/drain regions 42 a of the low withstand voltage n-channel transistor 42 are similarly formed in a step similar to the step of ion-implanting P (phosphorus) according to the aforementioned first modification shown in FIG. 15. In a step similar to the step according to the aforementioned first modification shown in FIG. 16, P (phosphorus) is ion-implanted while covering the region of the selection transistor 41 formed with the source region 41 b (17) (see FIG. 22) with a resist film. Thus, an impurity region 14 b is formed in the drain region 41 a while no impurity region 14 b is formed in the source region 41 b (17) in the source/drain regions 41 b (17) (see FIG. 22) and 41 a on the region formed with the selection transistor 41. In a subsequent step similar to the step according to the aforementioned first modification shown in FIG. 18, As is similarly ion-implanted into the regions of the selection transistor 41 and the low withstand voltage n-channel transistor 42 formed with the source region 41 b (17) and the source/drain regions 42 a respectively while covering the region of the selection transistor 41 formed with the drain region 41 a with a resist film and opening the region formed with the source region 41 b (17) (see FIG. 22). Thus, a high-concentration impurity region 17 b (see FIG. 22) of the same depth as n-type high-concentration impurity regions 42 c of the n-type source/drain regions 42 a of the low withstand voltage n-channel transistor 42 is formed in the source region 41 b (17) of the selection transistor 41. According to the second modification of the first embodiment, the selection transistor 41 shown in FIG. 22 can be formed through a fabrication process similar to that according to the aforementioned first modification except the above steps.

Second Embodiment

The structure of an MRAM (magnetic random access memory) according to a second embodiment of the present invention is now described with reference to FIGS. 23 to 28. The second embodiment is described with reference to an example of forming a drain region 66 of each selection transistor 61 and a cathode of a diode 50 included in each memory cell 59 by a common impurity region in a crosspoint MRAM.

In the MRAM according to the second embodiment, each memory cell 59 arranged on a memory cell array 56 comprises a single diode 60 and a single TMR (tunneling magnetoresistance) element 62, as shown in FIG. 23. The TMR element 62 has a first electrode connected to the anode of the diode 50 and a second electrode connected to a corresponding bit line (BL) 8. The remaining circuit structure of the MRAM according to the second embodiment is similar to that of the mask ROM according to the aforementioned first embodiment.

As shown in FIGS. 24 and 25, the TMR element 62 is formed by holding a nonmagnetic layer 62 a consisting of a thin oxide film (alumina) by a pin layer 62 b and a free layer 62 c of magnetic substances. The pin layer 62 b is constituted of a magnetic layer having a hardly changing magnetic direction. The free layer 62 c is constituted of a magnetic layer having an easily changing magnetic direction. The TMR element 62 is so formed that the quantity of current flowing therethrough varies with the magnetic directions of the pin layer 62 b and the free layer 62 c. In other words, resistance of the TMR element 62 is reduced to increase the quantity of current I₀ (see FIG. 24) flowing through the TMR element 62 when the magnetic directions of the pin layer 62 b and the free layer 62 c are identical to each other. When the magnetic directions of the pin layer 62 b and the free layer 62 c are different from each other, on the other hand, the resistance of the TMR element 62 is increased to reduce the quantity of current I₁ (see FIG. 25) flowing through the TMR element 62.

In the memory cell array 56 of the MRAM according to the second embodiment, a plurality of n-type impurity regions 64 containing P (phosphorus) are formed on the upper surface of a p-type silicon substrate 13 at prescribed intervals, as shown in FIGS. 26 and 27. The n-type impurity regions 64 are examples of the “first impurity region” in the present invention. Further, p-type impurity regions 65 containing B (boron) are formed in the n-type impurity regions 64. The p-type impurity regions 65 and the n-type impurity regions 64 constitute the diodes 60. Selection transistors 61 are provided on both sides of the n-type impurity regions 64 along the longitudinal direction of the n-type impurity regions 64, as shown in FIG. 27.

According to the second embodiment, each n-type impurity region 64 is employed in common as the cathodes of a plurality of (eight) diodes 60 and drain regions 66 of the corresponding selection transistors 61. N-type source regions 67 of the selection transistors 61 are provided on the upper surface of the p-type silicon substrate 13 at prescribed intervals from the n-type impurity region 64. Further, n-type contact regions 67 c are formed in the n-type source regions 67 for reducing contact resistance following connection of first plugs 23 to the n-type source regions 67. Gate electrodes 69 of polysilicon are provided on channel regions between the n-type impurity region 64 and the source regions 67 through gate insulating films 68.

As shown in FIG. 26, an element separation insulating film 70 of silicon oxide is formed between each pair of n-type impurity regions 64 adjacent to each other along the longitudinal direction of the bit lines BL. Word lines 7 of polysilicon are provided on such element separation insulating films 70. The aforementioned gate electrodes 69 are formed integrally with the corresponding word lines 7. Lining wires 71 of Al for the word lines 7 are provided on a first interlayer dielectric film 21 provided on the upper surface of the p-type silicon substrate 13 to cover the word lines 7 in correspondence to the word lines 7, as shown in FIGS. 26 and 27. The lining wires 71 are connected to the corresponding word lines 7 through plugs (not shown) on prescribed regions.

The TMR element 62 having the aforementioned structure is provided on a second interlayer dielectric film 25 formed on the first interlayer dielectric film 21. The pin layer 62 b of the TMR element 62 is connected to the corresponding p-type impurity region 65 (anode of the diode 60) through the corresponding first plug 23, a connection layer 24 and a second plug 26. A bit line 8 of Al is formed on the free layer 62 c of the TMR element 62. This bit line 8 is formed to extend perpendicularly to the longitudinal direction of the lining wires 61 for the word lines 7.

The remaining structure of the MRAM according to the second embodiment is similar to that of the mask ROM according to the aforementioned first embodiment.

Operations of the MRAM according to the second embodiment are now described with reference to FIG. 26.

In order to rewrite data in the MRAM according to the second embodiment, currents perpendicular to each other are fed to a prescribed bit line 8 and the lining wire 71 for the corresponding word line 7. Thus, data of only the TMR element 62 located on the intersection between the bit line 8 and the lining wire 71 can be rewritten. More specifically, the currents flowing to the lining wire 71 and the bit line 8 generate magnetic fields so that the sum (composite magnetic field) of the two magnetic fields acts on the TMR element 62. The magnetic direction of the free layer 62 c of the TMR element 62 is inverted due to the composite magnetic field. Thus, the data held in the TMR element 62 is rewritten from “1” to “0”, for example. In order to read data from the MRAM according to the second embodiment, a sense amplifier 4 determines data “0” or “1” on the basis of change of a current flowing due to resistance change of the TMR element 62. The remaining read operation is similar to that of the mask ROM according to the aforementioned first embodiment.

According to the second embodiment, as hereinabove described, the memory cell size can be reduced in the MRAM having the TMR elements 62 provided on the diodes 10, while the structure of and a fabrication process for a memory cell array region can be simplified.

The remaining effects of the second embodiment are similar to those of the aforementioned first embodiment.

The structure of an MRAM according to a modification of the second embodiment is now described with reference to FIGS. 29 to 31.

The MRAM according to the modification of the second embodiment is so constituted as to rewrite data of a prescribed TMR element 92 by directly feeding a current to a pin layer 92 d of the TMR element 92, dissimilarly to the MRAM according to the aforementioned second embodiment. More specifically, each TMR element 92 has a pin layer 92 b and the pin layer 92 d divided from each other. The pin layer 92 b is connected to a corresponding p-type impurity region 65 (anode of a diode 60) through a plug 23, as shown in FIGS. 29 and 30. The other pin layer 92 d is formed to extend perpendicularly to the longitudinal direction of bit lines 8, as shown in FIG. 31. The pin layer 92 d is connected to a plug (not shown) connected to a corresponding word line 7 on a prescribed region. According to the modification of the second embodiment, no lining wire 71 (see FIG. 26) is provided for the word line 7. The remaining structure of the MRAM according to the modification of the second embodiment is similar to that of the MRAM according to the aforementioned second embodiment.

Operations of the MRAM according to the modification of the second embodiment are now described. In order to rewrite data, the MRAM according to the modification of the second embodiment feeds currents perpendicular to each other to a prescribed bit line 8 and the pin layer 92 d of the corresponding TMR element 92. Thus, the currents flowing to the bit line 8 and the pin layer 92 d generate magnetic fields so that the composite magnetic field of the two magnetic fields inverts the magnetic direction of a free layer 92 c. Thus, the data held in the TMR element 92 is rewritten from “1” to “0”, for example. The remaining operations of the MRAM according to the modification of the second embodiment are similar to those of the MRAM according to the aforementioned second embodiment.

According to the modification of the second embodiment, as hereinabove described, the MRAM feeds the current to the pin layer 92 d of the prescribed TMR element 92 for rewriting data, so that the pin layer 92 d close to the free layer 92 c can generate a magnetic field. Also when feeding a small current to the pin layer 92 d, the MRAM can sufficiently invert the magnetic direction of the free layer 92, for efficiently rewriting the data of the TMR element 92 with the small current.

Third Embodiment

FIG. 32 is a plane layout diagram showing the structure of a mask ROM according to a third embodiment of the present invention. FIG. 33 is an enlarged plan view showing a region D, illustrated with broken lines, of the mask ROM according to the third embodiment shown in FIG. 32 in an enlarged manner. The structure of the mask ROM according to the third embodiment of the present invention is now described with reference to FIGS. 32 and 33.

In the mask ROM according to the third embodiment, regions of n-type impurity regions 114 serving as drain regions and source regions 117 in the vicinity of portions intersecting with gate electrodes 19 a on regions formed with selection transistors 11 a are arranged to obliquely extend at an angle θ (not more than about 40°) with respect to the longitudinal direction of the n-type impurity regions 114 on a region formed with memory cells 9 similar to that shown in FIG. 1 in plan view as shown in FIGS. 32 and 33, dissimilarly to the aforementioned mask ROM according to the first embodiment. The n-type impurity regions 114 are examples of the “first impurity region” in the present invention, and the source regions 117 are examples of the “second impurity region” in the present invention. Further, regions of the n-type impurity regions 114 serving as the drain regions and the source regions 117 in the vicinity of the portions intersecting with the gate electrodes 19 a on the regions formed with the selection transistors 11 a are arranged to obliquely extend oppositely to the oblique longitudinal direction of the gate electrodes 19 a of the selection transistors 11 a in plan view. Thus, the mask ROM according to the third embodiment is so constituted that the n-type impurity regions 114 and the gate electrodes 19 a of the selection transistors 11 a intersect with each other on the regions formed with the selection transistors 11 a at a deeper angle as compared with the mask ROM according to the first embodiment shown in FIG. 2.

Further, regions of the n-type impurity regions 114 serving as the drain regions and the source regions 117 in the vicinity of portions intersecting with gate electrodes 19 b on regions formed with selection transistors 11 b are arranged to obliquely extend at the angle θ (not more than about 40°) with respect to the longitudinal direction of the n-type impurity regions 114 on the region formed with the memory cells 9 similar to that shown in FIG. 1 in plan view. In addition, the regions of the n-type impurity regions 114 serving as the drain regions and the source regions 117 in the vicinity of the portions intersecting with the gate electrodes 19 b on the regions formed with the selection transistors 11 b are arranged to obliquely extend oppositely to the oblique longitudinal direction of the gate electrodes 19 b of the selection transistors 11 b in plan view. Thus, the mask ROM according to the third embodiment is so constituted that the n-type impurity regions 114 and the gate electrodes 19 b of the selection transistors 11 b intersect with each other on the regions formed with the selection transistors 11 b at a deeper angle as compared with the mask ROM according to the first embodiment shown in FIG. 2.

According to the third embodiment, two opposite sides of each gate electrode 19 are constituted of portions (portions E and F in FIG. 33) having angles of about 45° and about 40° with respect to the direction along each n-type impurity region 114 respectively in plan view, as shown in FIG. 33. Thus, the width t11 of a portion of the gate electrode 19 connected with a corresponding word line 7 in a direction substantially perpendicular to the longitudinal direction of the gate electrode 19 is smaller than the width t12 of a portion around the center of the gate electrode 19 in the direction substantially perpendicular to the longitudinal direction of the gate electrode 19. According to this structure, the portions, having the angle of about 40°, of each gate electrode 19 around the portion, having the width t11, connected with the word line 7 are opposed to other gate electrodes 19 adjacent thereto while the interval between each pair of gate electrodes 19 is increased, whereby the regions of each gate electrode 19 in the vicinity of the portion connected with the word line 7 are inhibited from coming into contact with the gate electrodes 19 adjacent thereto. As shown in FIG. 33, further, the width t13 of each word line 7 in a direction substantially perpendicular to the longitudinal direction of each n-type impurity region 114 is smaller than the width t12 of the portion around the center of the corresponding gate electrode 19 in the direction substantially perpendicular to the longitudinal direction of the gate electrode 19 on the region formed with the memory cells 9 similar to that according to the first embodiment shown in FIG. 1.

According to the third embodiment, the n-type impurity regions 114 and the source regions 117 are arranged to have inverted U shapes intersecting with the U shapes of the gate electrodes 19 a, connecting portions 19 c and the gate electrodes 19 b in plan view on the regions formed with the selection transistors 11 a and 11 b. Further, edges of the connecting portions 19 c opposite to the source regions 117 and edges of the n-type impurity regions 114 opposite to the word lines 7 on the region formed with the memory cells 9 similar to that shown in FIG. 1 are substantially aligned with each other. In addition, edges of the source regions 117 opposite to the connecting portions 19 c and edges of the word lines 7 opposite to the n-type impurity regions 114 on the region formed with the memory cells 9 similar to that shown in FIG. 1 are also substantially aligned with each other.

The remaining structure of the mask ROM according to the third embodiment is similar to that of the aforementioned mask ROM according to the first embodiment.

According to the third embodiment, as hereinabove described, the regions of the n-type impurity regions 114 serving as the drain regions and the source regions 117 in the vicinity of the portions intersecting with the gate electrodes 19 a on the regions formed with the selection transistors 11 a are arranged to obliquely extend with respect to the longitudinal direction of the n-type impurity regions 114 on the region formed with the memory cells 9 similar to that shown in FIG. 1 in plan view so that the n-type impurity regions 114 and the gate electrodes 19 a intersect with each other in obliquely inclined states in plan view on the regions formed with the selection transistors 11 a, whereby the n-type impurity regions 114 and the gate electrodes 19 a can intersect with each other at a deeper angle on the regions formed with the selection transistors 11 a. Further, the regions of the n-type impurity regions 114 serving as the drain regions and the source regions 117 in the vicinity of the portions intersecting with the gate electrodes 19 b on the regions formed with the selection transistors 11 b are arranged to obliquely extend with respect to the longitudinal direction of the n-type impurity regions 114 on the region formed with the memory cells 9 similar to that shown in FIG. 1 in plan view so that the n-type impurity regions 114 and the gate electrodes 19 b intersect with each other in obliquely inclined states in plan view on the regions formed with the selection transistors 11 b, whereby the n-type impurity regions 114 and the gate electrodes 19 b can intersect with each other at a deeper angle on the regions formed with the selection transistors 11 b. The n-type impurity regions 114 can intersect with the gate electrodes 19 a and 19 b at deeper angles on the regions formed with the selection transistors 11 a and 11 b as hereinabove described, whereby the length (L in FIG. 32) of the regions formed with the selection transistors 11 a and 11 b along the longitudinal direction of the word lines 7 can be reduced. Thus, the selection transistors 11 a and 11 b can be reduced in size, whereby the mask ROM can be further miniaturized.

According to the third embodiment, further, the edges of the connecting portions 19 c opposite to the source regions 117 and the edges of the n-type impurity regions 114 opposite to the word lines 7 on the region formed with the memory cells 9 are substantially aligned with each other while the edges of the source regions 117 opposite to the connecting portions 19 c and the edges of the word lines 7 opposite to the n-type impurity regions 114 on the region formed with the memory cells 9 are also substantially aligned with each other so that the edges of the connecting portions 19 c opposite to the source regions 117 can be inhibited from projecting beyond the n-type impurity regions 114 on the region formed with the memory cells 9 while the edges of the source regions 117 opposite to the connecting portions 19 c can be inhibited from projecting beyond the word lines 7 on the region formed with the memory cells 9 on the outer peripheral portion of a memory cell array 6. Thus, the memory cell array 6 can be inhibited from size increase.

The remaining effects of the third embodiment are similar to those of the aforementioned first embodiment.

Although the present invention has been described and illustrated in detail, it is clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation, the spirit and scope of the present invention being limited only by the terms of the appended claims.

For example, while the present invention is applied to a crosspoint mask ROM or an MRAM in each of the aforementioned embodiments, the present invention is not restricted to this but is widely applicable to a crosspoint memory or a non-crosspoint memory other than the mask ROM or the MRAM. More specifically, while the second embodiment has been described with reference to the MRAM employing the TMR elements as elements with resistance change, the present invention is not restricted to this but may alternatively be applied to a memory employing elements other than TMR elements as those with resistance change. For example, the present invention may be applied to an OUM (ovonic unified memory) employing elements thermally switched between amorphous and crystalline states accompanying change of resistance values or an RRAM (resistance random access memory) employing CMR (colossal magnetoresistive) elements having resistance values remarkably changed upon application of a voltage pulse.

While each n-type impurity region 14 constituting the cathode of the diode 10 is constituted of the low-concentration impurity region 14 a and the impurity region 14 b having the impurity concentration slightly higher than that of the impurity region 14 a in the aforementioned first embodiment, the present invention is not restricted to this but the impurity regions 14 a and 14 b of the n-type impurity region 14 may alternatively have substantially identical impurity concentrations. Further, the n-type impurity region 14 may alternatively be composed of only the impurity region 14 a. In this case, ion implantation conditions are preferably set to form the corresponding p-type impurity regions 15 in the impurity region 14 a. Further, each memory can alternatively be formed while exchanging the conductive types of the p- and n-type regions in each of the aforementioned embodiments and the modifications thereof. 

1. A memory comprising: a memory cell array region including a plurality of memory cells arranged in the form of a matrix; a first selection transistor and a second selection transistor provided for the respective ones of said plurality of memory cells; a first impurity region functioning as an electrode partially constituting each said memory cell while functioning also as one of source/drain regions of said first selection transistor and said second selection transistor; a second impurity region functioning as the other one of said source/drain regions of said first selection transistor and said second selection transistor; and a word line provided on said memory cell array region along said first impurity region, wherein said first selection transistor and said second selection transistor share said second impurity region, a first gate electrode of said first selection transistor and a second gate electrode of said second selection transistor are provided integrally with said word line and arranged to obliquely extend with respect to the longitudinal direction of said first impurity region on a region formed with said memory cells and to intersect with said first impurity region on regions formed with said first selection transistor and said second selection transistor in plan view, and said first selection transistor and said second selection transistor divide said first impurity region.
 2. The memory according to claim 1, wherein two said word lines provided along divided said first impurity region respectively are connected with each other through said first gate electrode and said second gate electrode.
 3. The memory according to claim 1, wherein said first impurity region and said second impurity region are formed by performing ion implantation into a semiconductor substrate through said first gate electrode and said second gate electrode serving as masks.
 4. The memory according to claim 1, wherein regions of said first impurity region and said second impurity region at least in the vicinity of portions intersecting with said first gate electrode on said region formed with said first selection transistor are arranged to extend along the longitudinal direction of said first impurity region on said region formed with said memory cells in plan view, and regions of said first impurity region and said second impurity region at least in the vicinity of portions intersecting with said second gate electrode on said region formed with said second selection transistor are arranged to extend along the longitudinal direction of said first impurity region on said region formed with said memory cells in plan view.
 5. The memory according to claim 1, wherein regions of said first impurity region and said second impurity region at least in the vicinity of portions intersecting with said first gate electrode on said region formed with said first selection transistor are arranged to obliquely extend with respect to the longitudinal direction of said first impurity region on said region formed with said memory cells in plan view, and regions of said first impurity region and said second impurity region at least in the vicinity of portions intersecting with said second gate electrode on said region formed with said second selection transistor are arranged to obliquely extend with respect to the longitudinal direction of said first impurity region on said region formed with said memory cells in plan view.
 6. The memory according to claim 5, wherein said regions of said first impurity region and said second impurity region at least in the vicinity of said portions intersecting with said first gate electrode on said region formed with said first selection transistor are arranged to obliquely extend at an angle of not more than about 40° with respect to the longitudinal direction of said first impurity region on said region formed with said memory cells in plan view, and said regions of said first impurity region and said second impurity region at least in the vicinity of said portions intersecting with said second gate electrode on said region formed with said second selection transistor are arranged to obliquely extend at an angle of not more than about 40° with respect to the longitudinal direction of said first impurity region on said region formed with said memory cells in plan view.
 7. The memory according to claim 5, wherein said regions of said first impurity region and said second impurity region at least in the vicinity of said portions intersecting with said first gate electrode on said region formed with said first selection transistor are arranged to obliquely extend oppositely to the oblique longitudinal direction of said first gate electrode in plan view, and said regions of said first impurity region and said second impurity region at least in the vicinity of said portions intersecting with said second gate electrode on said region formed with said second selection transistor are arranged to obliquely extend oppositely to the oblique longitudinal direction of said second gate electrode in plan view.
 8. The memory according to claim 5, wherein said first gate electrode and said second gate electrode adjacent to each other are connected with each other through a connecting portion, an edge of said connecting portion opposite to said second impurity region and an edge of said first impurity region opposite to said word line on said region formed with said memory cells are substantially aligned with each other, and an edge of said second impurity region opposite to said connecting portion and an edge of said word line opposite to said first impurity region on said region formed with said memory cells are substantially aligned with each other.
 9. The memory according to claim 8, wherein said first gate electrode, said connecting portion and said second gate electrode are arranged to have U shapes in plan view, and said first impurity region and said second impurity region on said regions formed with said first selection transistor and said second selection transistor are arranged to have inverted U shapes intersecting with said U shapes of said first gate electrode, said connecting portion and said second gate electrode in plan view.
 10. The memory according to claim 1, wherein the width of said word line provided along said first impurity region in a direction substantially perpendicular to the longitudinal direction of said first impurity region on said region formed with said memory cells is smaller than the width of a portion around the center of said first gate electrode in a direction substantially perpendicular to the longitudinal direction of said first gate electrode and the width of a portion around the center of said second gate electrode in a direction substantially perpendicular to the longitudinal direction of said second gate electrode.
 11. The memory according to claim 1, wherein the width of a portion of said first gate electrode connected with said word line in a direction substantially perpendicular to the longitudinal direction of said first gate electrode is smaller than the width of a portion around the center of said first gate electrode in said direction substantially perpendicular to the longitudinal direction of said first gate electrode, and the width of a portion of said second gate electrode connected with said word line in a direction substantially perpendicular to the longitudinal direction of said second gate electrode is smaller than the width of a portion around the center of said second gate electrode in said direction substantially perpendicular to the longitudinal direction of said second gate electrode.
 12. The memory according to claim 11, wherein two opposite sides of said first gate electrode include a portion having a first angle with respect to the longitudinal direction of said first impurity region on said region formed with said memory cells and another portion having a second angle smaller than said first angle in plan view, and two opposite sides of said second gate electrode include a portion having said first angle with respect to the longitudinal direction of said first impurity region on said region formed with said memory cells and another portion having said second angle smaller than said first angle in plan view.
 13. The memory according to claim 1, wherein said plurality of memory cells include single diodes respectively, and said first impurity region of a first conductivity type functions as a common first electrode for said diodes of said plurality of memory cells.
 14. A memory comprising: a memory cell array region including a plurality of memory cells arranged in the form of a matrix; a first selection transistor and a second selection transistor provided for the respective ones of said plurality of memory cells; a first impurity region functioning as an electrode partially constituting each said memory cell while functioning also as one of source/drain regions of said first selection transistor and said second selection transistor; a second impurity region functioning as the other one of said source/drain regions of said first selection transistor and said second selection transistor; and a word line provided on said memory cell array region along said first impurity region, wherein said first selection transistor and said second selection transistor share said second impurity region, a first gate electrode of said first selection transistor and a second gate electrode of said second selection transistor are provided integrally with said word line and arranged to obliquely extend with respect to the longitudinal direction of said first impurity region on a region formed with said memory cells and to intersect with said first impurity region on regions formed with said first selection transistor and said second selection transistor in plan view, said first selection transistor and said second selection transistor divide said first impurity region, regions of said first impurity region and said second impurity region at least in the vicinity of portions intersecting with said first gate electrode on said region formed with said first selection transistor are arranged to obliquely extend with respect to the longitudinal direction of said first impurity region on said region formed with said memory cells in plan view, and regions of said first impurity region and said second impurity region at least in the vicinity of portions intersecting with said second gate electrode on said region formed with said second selection transistor are arranged to obliquely extend with respect to the longitudinal direction of said first impurity region on said region formed with said memory cells in plan view. 